Bricologica

Blog Hosting Change

Sun, 24 Jan 2016 23:13:00 -0800

This blog is now being hosted on bricologica.com–my home site which is brand new after dumping Wordpress and starting to use Jekyll.

It’s been a while since I’ve worked on the Z-80. It’s working. I switched over so some other things for a while. I started working on a symbolic debugger for the Z-80 but it is not too far yet. Also, did a 7 segment RGB display project where I used the Arduino to program an AtTiny to change the segments colors.

The purpose of the Z-80 project was to demonstrate to myself that I could still design, build, and troubleshoot low level embedded software, and I accomplished that.

Ideas for extending this project: 1) learn PCB layout and construction and redo with surface mount parts 2) finish the symbolic debugger 3) add VGA video 4) get SD card reader working

But for now, I’m launching my job search to do all this fun stuff while receiving a paycheck….

Board Works Without Arduino

Sun, 08 Nov 2015 12:20:00 -0800

I have been dealing with my board with its attached Arduino. And while I need the Arduino to unbrick the board, I don’t need it for normal operation.

It took me a while to figure out what was going on. The behavior depended on whether the start up function did a run from RAM. That is, copy the current bank 0 into a RAM bank and then swap that RAM bank into bank 0. This is needed to program flash since programming flash requires no access from flash while it’s programming. It is also necessary for setting breakpoints as a breakpoint is set by putting an ‘rst 20h’ instruction where the breakpoint belongs.

So when I was trying to run from RAM, it just bricked the computer. I finally recalled a choice I made to keep the CPLD from getting too complex. RESET changes the current banks, but I decided to rely on SW to set the next bank registers. But the runFromRAM function was just assuming that banks 2 and 3 were the same as the registers that specify the next banks 2 and 3. This is an invalid assumption. So, I added a memBankInit function that copies the current bank registers into the next bank registers.

Board Stopped Working

Fri, 30 Oct 2015 21:52:00 -0700

So, every so often my board decides to stop working. While it’s a problem, solving problems is fun. I did load a new image into the 0 bank that was aggressively optimized. So it could be that. I did reset after loading, but neglected to power cycle. When I turned it on last night, nothing.

So I decided to restore an old image–but the Arduino program wasn’t working. I am having trouble with wire wraps to bare copper wires. So I decided to redo the Arduino connector. I had been meaning to anyway, since I don’t need the Arduino anymore except with this happens. I also wanted to mount an SD card slot for accessing an SD card which could potentially give be a whole chunk of flash depending on if I can drivers to fit. I probably would use as a block addressable device rather than with a file system. Fortunately, linux has a command called “dd” which would let me do that.

Here are pictures of the new sections. The first is the connector with the Arduino already connected with the red wires. It also has the SD card slot.

This is the back. I had to solder the wires to the connector and the insulation is a bit melted, so I’m hoping I won’t have any shorts. Right now I don’t.

Now, I’m off to see if I can get the flash to program again….

Disassembler in Action

Wed, 28 Oct 2015 12:20:00 -0700

I have a mechanism for attaching the disassembler to the breakpoint prompt. The applet in bank 1 has to have the disassember code because it’s too big to fit with everything in bank 0. So, the address of the function is placed at 0x0024 and if that location is not 0, it is called. This has to be registered in main, so when the breakpoint occurs at the beginning of main, the disassember is not hooked up yet. But, see the output below. Once the debugger gets to 4074 disassembly is possible. The command is ‘z’ with optional number of instructions and then an optional start address. I still have a lot of diagnostic stuff in the breakpoint code that I’m ready to remove (e.g. “Set BP0 @ 4062 (6-0)” and “RST 20 to dd @ 4066”).

  1 Mark Hamann's Z80 Computer
  2 App Build: 20:59:21 Oct  1 2015
  3 BSP Build: 20:59:19 Oct  1 2015
  4 C Lib Build: 20:08:20 Sep 30 2015
  5 Menu
  6  1: dir
  7  2: run applet
  8  3: program intel hex
  9  4: utils menu
 10  5: drivers menu
 11 > 3
 12 In IHX program mode. Ensure that HW flow control is on.
 13 Flash bank to program (0-f)? 4
 14 Is this an applet (y/n)? n
 15 Not erased. Erase (y/n)? y
 16 Now, paste the .ihx contents
 17 The mode will end on the :00000001FF
 18 ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffDone!
 19 > 2
 20 Applet bank? (2-f)? c
 21 Loading C vector bank 4 and applet bank c for version 0103 (ok=0)
 22 Flash to RAM...
 23 Prepping banks...
 24 About to jump...
 25 Set BP0 @ 4060 (6-0)
 26 RST 20 to dd @ 4060
 27 Breaking at main()
 28 4060 e7
 29 RST 20 from dd @ 4060
 30 (brk @ 4060)> n
 31 branch 00
 32 Set BP0 @ 4062 (6-0)
 33 RST 20 to dd @ 4062
 34 RST 20 from dd @ 4062
 35 (brk @ 4062)>
 36 (brk @ 4062)> n
 37 branch 00
 38 Set BP0 @ 4066 (6-0)
 39 RST 20 to dd @ 4066
 40 RST 20 from dd @ 4066
 41 (brk @ 4066)> n
 42 branch 00
 43 Set BP0 @ 4068 (6-0)
 44 RST 20 to 21 @ 4068
 45 RST 20 from 21 @ 4068
 46 (brk @ 4068)> n
 47 branch 00
 48 Set BP0 @ 406b (6-0)
 49 RST 20 to 39 @ 406b
 50 RST 20 from 39 @ 406b
 51 (brk @ 406b)> n
 52 branch 00
 53 Set BP0 @ 406c (6-0)
 54 RST 20 to f9 @ 406c
 55 RST 20 from f9 @ 406c
 56 (brk @ 406c)> n
 57 branch 00
 58 Set BP0 @ 406d (6-0)
 59 RST 20 to 21 @ 406d
 60 RST 20 from 21 @ 406d
 61 (brk @ 406d)> n
 62 branch 00
 63 Set BP0 @ 4070 (6-0)
 64 RST 20 to e5 @ 4070
 65 RST 20 from e5 @ 4070
 66 (brk @ 4070)> z
 67 (brk @ 4070)> n
 68 branch 00
 69 Set BP0 @ 4071 (6-0)
 70 RST 20 to cd @ 4071
 71 RST 20 from cd @ 4071
 72 (brk @ 4071)> z
 73 (brk @ 4071)> n
 74 branch 18
 75 Set BP0 @ 4074 (6-0)
 76 RST 20 to 21 @ 4074
 77 RST 20 from 21 @ 4074
 78 (brk @ 4074)> z
 79 4074: ld hl, 8080h
 80 4077: ex (sp), hl
 81 4078: call 3f23h
 82 407b: pop af
 83 407c: call 3f1dh
 84 407f: ld hl, 007fh
 85 4082: push hl
 86 4083: call 3f11h
 87 (brk @ 4074)> z 10 0
 88 0: jp 0069h
 89 3: rst 38h
 90 4: rst 38h
 91 5: rst 38h
 92 6: rst 38h
 93 7: rst 38h
 94 8: jp 0db1h
 95 b: rst 38h
 96 c: rst 38h
 97 d: rst 38h
 98 e: rst 38h
 99 f: rst 38h
100 10: jp 0dc2h
101 13: rst 38h
102 14: rst 38h
103 15: rst 38h
104 (brk @ 4074)> n
105 branch 00
106 Set BP0 @ 4077 (6-0)
107 RST 20 to e3 @ 4077
108 RST 20 from e3 @ 4077
109 (brk @ 4077)> z
110 4077: ex (sp), hl
111 4078: call 3f23h
112 407b: pop af
113 407c: call 3f1dh
114 407f: ld hl, 007fh
115 4082: push hl
116 4083: call 3f11h
117 4086: pop af
118 (brk @ 4077)> n
119 branch 00
120 Set BP0 @ 4078 (6-0)
121 RST 20 to cd @ 4078
122 RST 20 from cd @ 4078
123 (brk @ 4078)> n
124 branch 18
125 Set BP0 @ 407b (6-0)
126 RST 20 to f1 @ 407b
127 RST 20 from f1 @ 407b
128 (brk @ 407b)> z
129 407b: pop af
130 407c: call 3f1dh
131 407f: ld hl, 007fh
132 4082: push hl
133 4083: call 3f11h
134 4086: pop af
135 4087: ld hl, 0000h
136 408a: add hl, sp
137 (brk @ 407b)> c
138 branch 00
139 Set BP0 @ 407c (a-1)
140 RST 20 to cd @ 407c
141 RST 20 from cd @ 407c

OK, I cleaned up the diagnostic stuff. Here is what it looks like now:

 1 Menu
 2  1: dir
 3  2: run applet
 4  3: program intel hex
 5  4: utils menu
 6  5: drivers menu
 7 > 3
 8 In IHX program mode. Ensure that HW flow control is on.
 9 Flash bank to program (0-f)? 4
10 Is this an applet (y/n)? n
11 Not erased. Erase (y/n)? y
12 Now, paste the .ihx contents
13 The mode will end on the :00000001FF
14 fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffDone!
15 > 2
16 Applet bank? (2-f)? c
17 Loading C vector bank 4 and applet bank c for version 0103 (ok=0)
18 Flash to RAM...
19 Prepping banks...
20 About to jump...
21 Breaking at main()
22 4060 e7
23 (brk @ 4060)> n
24 (brk @ 4062)> n
25 (brk @ 4066)> n
26 (brk @ 4068)> n
27 (brk @ 406b)> n
28 (brk @ 406c)> n
29 (brk @ 406d)> n
30 (brk @ 4070)> n
31 (brk @ 4071)> n
32 (brk @ 4074)> n
33 (brk @ 4077)> z
34 4077: ex (sp), hl
35 4078: call 3f23h
36 407b: pop af
37 407c: call 3f1dh
38 407f: ld hl, 007fh
39 4082: push hl
40 4083: call 3f11h
41 4086: pop af
42 (brk @ 4077)> n
43 (brk @ 4078)> n
44 (brk @ 407b)> n
45 (brk @ 407c)> n
46 (brk @ 407f)> n
47 (brk @ 4082)> n
48 (brk @ 4083)> n
49 (brk @ 4086)> z
50 4086: pop af
51 4087: ld hl, 0000h
52 408a: add hl, sp
53 408b: ld d, l
54 408c: ld e, h
55 408d: ld bc, 40c7h
56 4090: push hl
57 4091: push de
58 (brk @ 4086)>

Disassembly

Mon, 26 Oct 2015 13:56:00 -0700

In order to make debugging easier, I thought it might to have a disassembler. It’s fairly table driven. It needs a lot of work still. I think it disassembles valid instructions, but doesn’t guarantee that invalid instructions are handled in any particular way. By valid, I mean the officially documented instructions. It is not optimized for speed. Rather, my goal was code size. Whether I met that or not is something I’m wondering. All the little special cases add code size.

Anyone needing a Z-80 disassembler is free to use what they want from this.

   1 // Associate shiftMask to a StartInfo
   2 struct ShiftMaskAndIndexStartInfo {
   3     // upper nibble is shift amount. Bottom nibble is mask
   4     uint8_t shiftMaskInfo;
   5 
   6     // A start index
   7     uint8_t indexStart;
   8 };
   9 
  10 // Information to create an instruction
  11 struct InstructionInfo
  12 {
  13     // 8 bit mask of relevant bits
  14     uint8_t mask;
  15 
  16     // expected value after anding with mask
  17     uint8_t value;
  18 
  19     // 7-6: type  5-0: index
  20     uint8_t opcodeInfo;
  21 
  22     // arg0 info
  23     uint8_t argInfoIndex0;
  24 
  25     // arg1 info
  26     uint8_t argInfoIndex1;
  27 };
  28 
  29 // Opcode builder
  30 struct OpcodeBuildInfo {
  31     // 8 bit mask of relevant bits
  32     uint8_t mask;
  33 
  34     // Expected value after anding with mask
  35     uint8_t value;
  36 
  37     // Letter to append if (b & mask) == value
  38     char letter;
  39 };
  40 
  41 
  42 // Keep synched with InstructionTableArray
  43 enum InstructionTableIndices
  44 {
  45     TABLE_MAIN_00,
  46     TABLE_MAIN_40,
  47     TABLE_MAIN_80,
  48     TABLE_MAIN_C0,
  49     TABLE_CB,
  50     TABLE_ED,
  51     TABLE_COUNT
  52 };
  53 
  54 // keep synched with LiteralStringArray
  55 enum LiteralStringIndices {
  56     DA_LIT_Q,
  57     DA_LIT_nop,
  58     DA_LIT_djnz,
  59     DA_LIT_jr,
  60     DA_LIT_ld,
  61     DA_LIT_add,
  62     DA_LIT_ex,
  63     DA_LIT_halt,
  64     DA_LIT_ret,
  65     DA_LIT_call,
  66     DA_LIT_jp,
  67     DA_LIT_exx,
  68     DA_LIT_rst,
  69     DA_LIT_neg,
  70     DA_LIT_reti,
  71     DA_LIT_retn,
  72     DA_LIT_im,
  73     DA_LIT_inc,
  74     DA_LIT_dec,
  75     DA_LIT_adc,
  76     DA_LIT_sub,
  77     DA_LIT_sbc,
  78     DA_LIT_and,
  79     DA_LIT_xor,
  80     DA_LIT_or,
  81     DA_LIT_cp,
  82     DA_LIT_daa,
  83     DA_LIT_cpl,
  84     DA_LIT_scf,
  85     DA_LIT_ccf,
  86     DA_LIT_pop,
  87     DA_LIT_push,
  88     DA_LIT_out,
  89     DA_LIT_in,
  90     DA_LIT_di,
  91     DA_LIT_ei,
  92     DA_LIT_bit,
  93     DA_LIT_set,
  94     DA_LIT_res,
  95     DA_LIT_nz,
  96     DA_LIT_z,
  97     DA_LIT_nc,
  98     DA_LIT_c,
  99     DA_LIT_po,
 100     DA_LIT_pe,
 101     DA_LIT_p,
 102     DA_LIT_m,
 103     DA_LIT_bc,
 104     DA_LIT_de,
 105     DA_LIT_hl,
 106     DA_LIT_ix,
 107     DA_LIT_iy,
 108     DA_LIT_sp,
 109     DA_LIT_af,
 110     DA_LIT_a,
 111     DA_LIT_b,
 112     DA_LIT_d,
 113     DA_LIT_e,
 114     DA_LIT_h,
 115     DA_LIT_l,
 116     DA_LIT_i,
 117     DA_LIT_r,
 118     DA_LIT_af_alt,
 119     DA_LIT_COUNT
 120 };
 121 
 122 // keep synced with enum DisassembleLiteralIndices
 123 static const char* const LiteralStringArray[DA_LIT_COUNT] =
 124 {
 125     "?",
 126     "nop",
 127     "djnz",
 128     "jr",
 129     "ld",
 130     "add",
 131     "ex",
 132     "halt",
 133     "ret",
 134     "call",
 135     "jp",
 136     "exx",
 137     "rst",
 138     "neg",
 139     "reti",
 140     "retn",
 141     "im",
 142     "inc",
 143     "dec",
 144     "adc",
 145     "sub",
 146     "sbc",
 147     "and",
 148     "xor",
 149     "or",
 150     "cp",
 151     "daa",
 152     "cpl",
 153     "scf",
 154     "ccf",
 155     "pop",
 156     "push",
 157     "out",
 158     "in",
 159     "di",
 160     "ei",
 161     "bit",
 162     "set",
 163     "res",
 164     "nz",
 165     "z",
 166     "nc",
 167     "c",
 168     "po",
 169     "pe",
 170     "p",
 171     "m",
 172     "bc",
 173     "de",
 174     "hl",
 175     "ix",
 176     "iy",
 177     "sp",
 178     "af",
 179     "a",
 180     "b",
 181     "d",
 182     "e",
 183     "h",
 184     "l",
 185     "i",
 186     "r",
 187     "af'"
 188 };
 189 
 190 /*
 191 0: @alu : add, adc, sub, sbc, and, xor, or, cp
 192 1 : @bitsetres : -, bit, set, res
 193 2 : @daacplscfccf : daa, cpl, scf, ccf
 194 3 : @incdec : inc, dec
 195 4 : @poppush : pop, push
 196 5 : @outin : out, in
 197 6 : @inout : in, out
 198 7 : @diei : di, ei
 199 8 : @sbcadc : sbc, adc
 200 */
 201 
 202 enum OpcodeByMaskInfoIndices
 203 {
 204     OPCODE_MASKABLE_ALU, // 10@@ @rrr -- 11@@ @110
 205     OPCODE_MASKABLE_BIT, // @@## #rrr
 206     OPCODE_MASKABLE_DAA, // 001@ @111
 207     OPCODE_MASKABLE_INC_RRS, // 00rr @011
 208     OPCODE_MASKABLE_INC_R, // 00rr r10@
 209     OPCODE_MASKABLE_POP, // 11rr 0@01
 210     OPCODE_MASKABLE_INOUT, // 01rr r00@
 211     OPCODE_MASKABLE_OUTIN, // 1110 @011
 212     OPCODE_MASKABLE_DIEI, // 1111 @011
 213     OPCODE_MASKABLE_SBC, // 01rr @010
 214     OPCODE_MASKABLE_COUNT,
 215 };
 216 
 217 enum OpcodeByMaskStartIndices
 218 {
 219     MASKABLE_ALU = 0,
 220     MASKABLE_BIT = MASKABLE_ALU + 8-1, // first element of bit can't exist, so collapse
 221     MASKABLE_DAA = MASKABLE_BIT + 4,
 222     MASKABLE_INC = MASKABLE_DAA + 4,
 223     MASKABLE_POP = MASKABLE_INC + 2,
 224     MASKABLE_INOUT = MASKABLE_POP + 2,
 225     MASKABLE_OUTIN = MASKABLE_INOUT + 2 - 1,
 226     MASKABLE_DIEI = MASKABLE_OUTIN + 2,
 227     MASKABLE_SBC = MASKABLE_DIEI + 2,
 228     MASKABLE_ARRAY_COUNT = MASKABLE_SBC + 2
 229 };
 230 
 231 static const struct ShiftMaskAndIndexStartInfo OpcodeByMaskShiftMaskArray[OPCODE_MASKABLE_COUNT] =
 232 {
 233     {
 234         0x37, MASKABLE_ALU
 235     },
 236     {
 237         0x63, MASKABLE_BIT
 238     },
 239     {
 240         0x33, MASKABLE_DAA
 241     },
 242     { // r
 243         0x31, MASKABLE_INC
 244     },
 245     { // rrs
 246         0x01, MASKABLE_INC
 247     },
 248     {
 249         0x21, MASKABLE_POP
 250     },
 251     {
 252         0x01, MASKABLE_INOUT
 253     },
 254     {
 255         0x31, MASKABLE_OUTIN
 256     },
 257     {
 258         0x31, MASKABLE_DIEI
 259     },
 260     {
 261         0x31, MASKABLE_SBC
 262     },
 263 };
 264 
 265 static const uint8_t OpcodeByMaskArray[MASKABLE_ARRAY_COUNT] =
 266 {
 267     // MASKABLE_ALU = 0
 268     DA_LIT_add, // 0
 269     DA_LIT_adc,
 270     DA_LIT_sub,
 271     DA_LIT_sbc,
 272     DA_LIT_and,
 273     DA_LIT_xor,
 274     DA_LIT_or,
 275     // MASKABLE_BIT = 7
 276     DA_LIT_cp,
 277 
 278     DA_LIT_bit, // 8
 279     DA_LIT_res,
 280     DA_LIT_set,
 281 
 282     // MASKABLE_DAA
 283     DA_LIT_daa, // 11
 284     DA_LIT_cpl,
 285     DA_LIT_scf,
 286     DA_LIT_ccf,
 287 
 288     // MASKABLE_INC
 289     DA_LIT_inc, // 15
 290     DA_LIT_dec,
 291 
 292     // MASKABLE_POP
 293     DA_LIT_pop, // 17
 294     DA_LIT_push,
 295 
 296     // MASKABLE_INOUT
 297     DA_LIT_in, // 19
 298     // MASKABLE_OUTIN
 299     DA_LIT_out, // 20
 300     DA_LIT_in,
 301 
 302     // MASKABLE_EIDI
 303     DA_LIT_di, // 22
 304     DA_LIT_ei,
 305 
 306     // MASKABLE_SBC
 307     DA_LIT_sbc, // 24
 308     DA_LIT_adc
 309 };
 310 
 311 // ROTATE Main-00-00; ED-80-00; CB-02-00 "r"
 312 // SHIFT CB-02-02 "s"
 313 // LD ED-07-00 "ld"
 314 // CP ED-07-01 "cp"
 315 // IN ED-07-02 "in"
 316 // OT ED-07-03 "ot
 317 // CARRY MAIN/CB-01-01 "c"
 318 // LOGIGAL CB-03-03 "l"
 319 // ARITH/Acc CB-03-02 "a"
 320 // LEFT Main-08-00; "l"
 321 // RIGHT Main-08-08; "r"
 322 // INC ED-88-80 "i"
 323 // DEC ED-88-88 "d"
 324 // REPEAT ED-f0-b0 "r"
 325 
 326 enum OpcodeByBuilderIndices
 327 {
 328     OPCODE_BUILD_RLCA,
 329     OPCODE_BUILD_RRD,
 330     OPCODE_BUILD_LDI,
 331     OPCODE_BUILD_RLC
 332 };
 333 
 334 // sync with OpcodeBuilderArray and OpcodeByBuilderIndices
 335 static const uint8_t OpcodeBuilderIndexToOpcodeBuilderArrayStartIndex[] = {
 336     0,
 337     6,
 338     11,
 339     24,
 340     33
 341 };
 342 
 343 // synch with OpcodeBuilderIndexToOpcodeBuilderArrayStartIndex
 344 static const struct OpcodeBuildInfo OpcodeBuilderArray[32] = {
 345     //MAIN table
 346     //{
 347     // main = 0 (5)
 348     { 0x00, 0x00, 'r' },
 349     { 0x08, 0x00, 'l' },
 350     { 0x08, 0x08, 'r' },
 351     { 0x10, 0x00, 'c' },
 352     { 0x00, 0x00, 'a' },
 353     { 0x00, 0x00, 0 },
 354     //},
 355     // ED table
 356     //{
 357     { 0x00, 0x00, 'r' },
 358     { 0xc8, 0x40, 'r' },
 359     { 0xc8, 0x48, 'l' },
 360     { 0x00, 0x00, 'd' },
 361     { 0x00, 0x00, 0 },
 362     //},
 363     //{
 364     { 0xc7, 0x80, 'l' },
 365     { 0xc7, 0x80, 'd' },
 366     { 0xc7, 0x81, 'c' },
 367     { 0xc7, 0x81, 'p' },
 368     { 0xc7, 0x82, 'i' },
 369     { 0xc7, 0x82, 'n' },
 370     { 0xc7, 0x83, 'o' },
 371     { 0xf7, 0xa3, 'u' },
 372     { 0xc7, 0x83, 't' },
 373     { 0x88, 0x80, 'i' },
 374     { 0x88, 0x88, 'd' },
 375     { 0xf0, 0xb0, 'r' },
 376     { 0x00, 0x00, 0 },
 377     //},
 378     // CB table
 379     //{
 380     { 0x20, 0x00, 'r' },
 381     { 0x20, 0x20, 's' },
 382     { 0x08, 0x00, 'l' },
 383     { 0x08, 0x08, 'r' },
 384     { 0x30, 0x00, 'c' },
 385     { 0x30, 0x20, 'a' },
 386     { 0x30, 0x30, 'l' },
 387     { 0x00, 0x00, 0 },
 388     //}
 389 };
 390 
 391 
 392 #define ARG_TYPE_SPECIAL    (0x00)
 393 #define ARG_TYPE_LIT        (0x10)
 394 #define ARG_TYPE_MASK       (0x20)
 395 #define ARG_TYPE_SWAPPABLE  (0x40)
 396 #define ARG_TYPE_CONTENTS   (0x80)
 397 
 398 enum ArgByMaskStartIndices
 399 {
 400     ARG_ARR_FL = 0,
 401     ARG_ARR_RRS = ARG_ARR_FL + 8,
 402     ARG_ARR_RRA = ARG_ARR_RRS + 4,
 403     ARG_ARR_HLA = ARG_ARR_RRA + 4,
 404     ARG_ARR_R = ARG_ARR_HLA + 2,
 405     ARG_ARR_IR = ARG_ARR_R + 8,
 406     ARG_ARR_IM = ARG_ARR_IR + 2,
 407     ARG_ARR_COUNT = ARG_ARR_IM + 4
 408 };
 409 
 410 static const uint8_t ArgByMaskArray[ARG_ARR_COUNT] =
 411 {
 412     DA_LIT_nz, // 0
 413     DA_LIT_z,
 414     DA_LIT_nc,
 415     DA_LIT_c,
 416     DA_LIT_po,
 417     DA_LIT_pe,
 418     DA_LIT_p,
 419     DA_LIT_m,
 420 
 421     DA_LIT_bc, // 8
 422     DA_LIT_de,
 423     DA_LIT_hl,
 424     DA_LIT_sp,
 425 
 426     DA_LIT_bc, // 12
 427     DA_LIT_de,
 428     DA_LIT_hl,
 429     DA_LIT_af,
 430 
 431     DA_LIT_hl, // 16
 432     DA_LIT_a,
 433 
 434     DA_LIT_b, // 18
 435     DA_LIT_c,
 436     DA_LIT_d,
 437     DA_LIT_e,
 438     DA_LIT_h,
 439     DA_LIT_l,
 440     DA_LIT_hl | ARG_TYPE_CONTENTS,
 441     DA_LIT_a,
 442 
 443     DA_LIT_i, // 42
 444     DA_LIT_r,
 445 };
 446 
 447 /*
 448 // 
 449 #define ARG_TYPE_MASK (0x01)
 450 // mask, index
 451 #define ARG_TYPE_LIT (0x02)
 452 // (int8_t)(*(pc)) + pc; pc++;
 453 #define ARG_TYPE_REL (0x03)
 454 #define ARG_TYPE_IMM8 (0x04)
 455 #define ARG_TYPE_IMM16 (0x05)
 456 #define ARG_TYPE_ASCII (0x06)
 457 #define ARG_TYPE_RST (0x07)
 458 */
 459 
 460 // index to next table ED/CB/DDFD
 461 #define OPCODE_TYPE_LIT (0x00)
 462 // index
 463 #define OPCODE_TYPE_ARR (0x40)
 464 // mask, index
 465 #define OPCODE_TYPE_BUILD (0x80)
 466 // index
 467 #define OPCODE_TYPE_SUB (0xc0)
 468 
 469 
 470 // [8:mask],[8:val],[2:opcode, 6:index0] [1: swappable 3: arg0 3: arg1]
 471 // index 0 is literal index for literal, or maskables index for maskable. For build, the build index
 472 // swapbit is there only if swappable. Swap bit is 3 for main, 4 for ED
 473 // arginfo is:
 474 //  if 00 no arg
 475 //  if 01 mask [8: mask(-sss-mmm)] [8: arg_arr index] or 3bit is mask index, 5 bits is arg_arr index
 476 //  if 02 lit [8: lit index]
 477 //  if 03 uint8 get next byte
 478 //  if 04 RelAddr get next byte, add to location
 479 //  if 05 uint16 get next word
 480 //  bit 8 swappable
 481 enum ArgInfo {
 482     ARG_INFO_NONE,
 483     ARG_INFO_rel, // 1
 484     ARG_INFO_imm8,
 485     ARG_INFO_imm16,
 486     ARG_INFO_bit,
 487     ARG_INFO_rst,
 488     ARG_INFO_im,
 489 
 490     ARG_INFO_LIT_a = ARG_TYPE_LIT, // 4
 491     ARG_INFO_LIT_af,
 492     ARG_INFO_LIT_af_alt,
 493     ARG_INFO_LIT_c,
 494     ARG_INFO_LIT_de,
 495 
 496     ARG_INFO_LIT_hl, // 8
 497     ARG_INFO_LIT_sp,
 498     //ARG_INFO_LIT_q,
 499 
 500     ARG_INFO_MASK_30_RRS = ARG_TYPE_MASK,
 501     ARG_INFO_MASK_30_RRA,
 502     ARG_INFO_MASK_07_R,
 503 
 504     ARG_INFO_MASK_38_R,
 505     ARG_INFO_MASK_18_FL,
 506     ARG_INFO_MASK_38_FL,
 507     ARG_INFO_MASK_08_IR,
 508 };
 509 
 510 /*
 511 enum ArgMaskIndex {
 512     ARG_MASK_30_RRS,
 513     ARG_MASK_30_RRA,
 514     ARG_MASK_07_R,
 515     ARG_MASK_38_R,
 516 
 517     ARG_MASK_30_FL,
 518     ARG_MASK_38_FL,
 519     ARG_MASK_38_RST,
 520     ARG_MASK_80_IR,
 521 
 522     ARG_MASK_COUNT,
 523 };
 524 */
 525 
 526 // sync with ArgInfo from ARG_TYPE_LIT
 527 static const uint8_t ArgByLitIndexToStringLiteralIndex[] = {
 528     DA_LIT_a,
 529     DA_LIT_af,
 530     DA_LIT_af_alt,
 531     DA_LIT_c,
 532 
 533     DA_LIT_de,
 534     DA_LIT_hl,
 535     DA_LIT_sp
 536 };
 537 
 538 // sync with ArgInfo from ARG_TYPE_MASK
 539 static const struct ShiftMaskAndIndexStartInfo ArgShiftMaskStartIndex[] =
 540 {
 541     { /*0x30*/ 0x43, ARG_ARR_RRS },
 542     { /*0x30*/ 0x43, ARG_ARR_RRA },
 543     { /*0x07*/ 0x07, ARG_ARR_R },
 544     { /*0x38*/ 0x37, ARG_ARR_R },
 545 
 546     { /*0x18*/ 0x33, ARG_ARR_FL },
 547     { /*0x38*/ 0x37, ARG_ARR_FL },
 548     { /*0x08*/ 0x31, ARG_ARR_IR },
 549 };
 550 
 551 char* buildOpcode(uint8_t opcode, uint8_t table, char* line)
 552 {
 553     const struct OpcodeBuildInfo* cand = &OpcodeBuilderArray[OpcodeBuilderIndexToOpcodeBuilderArrayStartIndex[table]];
 554     while (cand->letter != 0)
 555     {
 556         if ((opcode & cand->mask) == cand->value)
 557         {
 558             *line++ = cand->letter;
 559         }
 560         cand++;
 561     }
 562     *line++ = '\0';
 563     return line;
 564 }
 565 
 566 static const struct InstructionInfo InstructionInfoTableMain_00[] =
 567 {
 568     {
 569         0xff,
 570         0x00,
 571         DA_LIT_nop | OPCODE_TYPE_LIT,
 572         ARG_INFO_NONE,
 573         ARG_INFO_NONE,
 574     },
 575     {
 576         0xff,
 577         0x10,
 578         DA_LIT_djnz | OPCODE_TYPE_LIT,
 579         ARG_INFO_rel,
 580         ARG_INFO_NONE
 581     },
 582     {
 583         0xe7,
 584         0x20,
 585         DA_LIT_jr | OPCODE_TYPE_LIT,
 586         ARG_INFO_MASK_18_FL,
 587         ARG_INFO_rel,
 588     },
 589     {
 590         0xcf,
 591         0x01,
 592         DA_LIT_ld | OPCODE_TYPE_LIT,
 593         ARG_INFO_MASK_30_RRS,
 594         ARG_INFO_imm16
 595     },
 596     {
 597         0xe7,
 598         0x02,
 599         DA_LIT_ld | OPCODE_TYPE_LIT,
 600         ARG_INFO_MASK_30_RRS | ARG_TYPE_SWAPPABLE | ARG_TYPE_CONTENTS, // swap on 0x08
 601         ARG_INFO_LIT_a
 602     },
 603     {
 604         0xcf,
 605         0x09,
 606         DA_LIT_add | OPCODE_TYPE_LIT,
 607         ARG_INFO_LIT_hl,
 608         ARG_INFO_MASK_30_RRS
 609     },
 610     {
 611         0xf7,
 612         0x32,
 613         DA_LIT_ld | OPCODE_TYPE_LIT,
 614         ARG_INFO_imm16 | ARG_TYPE_SWAPPABLE | ARG_TYPE_CONTENTS, // swap on 0x08
 615         ARG_INFO_LIT_a
 616     },
 617     {
 618         0xf7,
 619         0x22,
 620         DA_LIT_ld | OPCODE_TYPE_LIT,
 621         ARG_INFO_imm16 | ARG_TYPE_SWAPPABLE | ARG_TYPE_CONTENTS, // swap on 0x08
 622         ARG_INFO_LIT_hl
 623     },
 624     {
 625         0xc7,
 626         0x03,
 627         OPCODE_MASKABLE_INC_RRS | OPCODE_TYPE_ARR,
 628         ARG_INFO_MASK_30_RRS,
 629         ARG_INFO_NONE
 630     },
 631     {
 632         0xc6,
 633         0x04,
 634         OPCODE_MASKABLE_INC_R | OPCODE_TYPE_ARR,
 635         ARG_INFO_MASK_38_R,
 636         ARG_INFO_NONE
 637     },
 638     {
 639         0xc7,
 640         0x06,
 641         DA_LIT_ld | OPCODE_TYPE_LIT,
 642         ARG_INFO_MASK_38_R,
 643         ARG_INFO_imm8
 644     },
 645     {
 646         0xff,
 647         0x08,
 648         DA_LIT_ex | OPCODE_TYPE_LIT,
 649         ARG_INFO_LIT_af,
 650         ARG_INFO_LIT_af_alt
 651     },
 652     {
 653         0xff,
 654         0x18,
 655         DA_LIT_jr | OPCODE_TYPE_LIT,
 656         ARG_INFO_rel,
 657         ARG_INFO_NONE
 658     },
 659     {
 660         0xe7,
 661         0x27,
 662         OPCODE_MASKABLE_DAA | OPCODE_TYPE_ARR,
 663         ARG_INFO_NONE,
 664         ARG_INFO_NONE
 665     },
 666     {
 667         0xe7,
 668         0x07,
 669         OPCODE_BUILD_RLCA | OPCODE_TYPE_BUILD,
 670         ARG_INFO_NONE,
 671         ARG_INFO_NONE
 672     },
 673     {
 674         0x00,
 675         0x00,
 676         DA_LIT_Q | OPCODE_TYPE_LIT,
 677         ARG_INFO_NONE,
 678         ARG_INFO_NONE
 679     }
 680 };
 681 static const struct InstructionInfo InstructionInfoTableMain_40[] =
 682 {
 683     { // Must be before ld r,r
 684         0xff,
 685         0x76,
 686         DA_LIT_halt | OPCODE_TYPE_LIT,
 687         ARG_INFO_NONE,
 688         ARG_INFO_NONE
 689     },
 690 
 691     { //  Must be after halt
 692         0xc0,
 693         0x40,
 694         DA_LIT_ld | OPCODE_TYPE_LIT,
 695         ARG_INFO_MASK_38_R,
 696         ARG_INFO_MASK_07_R
 697     },
 698     {
 699         0x00,
 700         0x00,
 701         DA_LIT_Q | OPCODE_TYPE_LIT,
 702         ARG_INFO_NONE,
 703         ARG_INFO_NONE
 704     }
 705 };
 706 static const struct InstructionInfo InstructionInfoTableMain_80[] =
 707 {
 708     {
 709         0xc0,
 710         0x80,
 711         OPCODE_MASKABLE_ALU | OPCODE_TYPE_ARR,
 712         ARG_INFO_LIT_a,
 713         ARG_INFO_MASK_07_R
 714     },
 715     {
 716         0x00,
 717         0x00,
 718         DA_LIT_Q | OPCODE_TYPE_LIT,
 719         ARG_INFO_NONE,
 720         ARG_INFO_NONE
 721     }
 722 };
 723 static const struct InstructionInfo InstructionInfoTableMain_c0[] =
 724 {
 725     {
 726         0xc7,
 727         0xc0,
 728         DA_LIT_ret | OPCODE_TYPE_LIT,
 729         ARG_INFO_MASK_38_FL,
 730         ARG_INFO_NONE
 731     },
 732     {
 733         0xff,
 734         0xcd,
 735         DA_LIT_call | OPCODE_TYPE_LIT,
 736         ARG_INFO_imm16,
 737         ARG_INFO_NONE
 738     },
 739     {
 740         0xff,
 741         0xc3,
 742         DA_LIT_jp | OPCODE_TYPE_LIT,
 743         ARG_INFO_imm16,
 744         ARG_INFO_NONE
 745     },
 746     {
 747         0xff,
 748         0xe9,
 749         DA_LIT_jp | OPCODE_TYPE_LIT,
 750         ARG_INFO_LIT_hl | ARG_TYPE_CONTENTS,
 751         ARG_INFO_NONE
 752     },
 753     {
 754         0xff,
 755         0xf9,
 756         DA_LIT_ld | OPCODE_TYPE_LIT,
 757         ARG_INFO_LIT_sp,
 758         ARG_INFO_LIT_hl
 759     },
 760     {
 761         0xcb,
 762         0xc1,
 763         OPCODE_MASKABLE_POP | OPCODE_TYPE_ARR,
 764         ARG_INFO_MASK_30_RRA,
 765         ARG_INFO_NONE
 766     },
 767     {
 768         0xff,
 769         0xc9,
 770         DA_LIT_ret | OPCODE_TYPE_LIT,
 771         ARG_INFO_NONE,
 772         ARG_INFO_NONE
 773     },
 774     {
 775         0xff,
 776         0xd9,
 777         DA_LIT_exx | OPCODE_TYPE_LIT,
 778         ARG_INFO_NONE,
 779         ARG_INFO_NONE
 780     },
 781     {
 782         0xc7,
 783         0xc2,
 784         DA_LIT_jp | OPCODE_TYPE_LIT,
 785         ARG_INFO_MASK_38_FL,
 786         ARG_INFO_imm16
 787     },
 788     {
 789         0xc7,
 790         0xc4,
 791         DA_LIT_call | OPCODE_TYPE_LIT,
 792         ARG_INFO_MASK_38_FL,
 793         ARG_INFO_imm16
 794     },
 795     {
 796         0xc7,
 797         0xc7,
 798         DA_LIT_rst | OPCODE_TYPE_LIT,
 799         ARG_INFO_rst,
 800         ARG_INFO_NONE
 801     },
 802     {
 803         0xc7,
 804         0xc6,
 805         OPCODE_MASKABLE_ALU | OPCODE_TYPE_ARR,
 806         ARG_INFO_LIT_a,
 807         ARG_INFO_imm8
 808     },
 809     {
 810         0xf7,
 811         0xd3,
 812         OPCODE_MASKABLE_OUTIN | OPCODE_TYPE_ARR,
 813         ARG_INFO_imm8 | ARG_TYPE_CONTENTS | ARG_TYPE_SWAPPABLE, // swap on 0x08
 814         ARG_INFO_LIT_a
 815     },
 816     {
 817         0xf7,
 818         0xf3,
 819         OPCODE_MASKABLE_DIEI | OPCODE_TYPE_ARR,
 820         ARG_INFO_NONE,
 821         ARG_INFO_NONE
 822     },
 823     {
 824         0xff,
 825         0xe3,
 826         DA_LIT_ex | OPCODE_TYPE_LIT,
 827         ARG_INFO_LIT_sp | ARG_TYPE_CONTENTS,
 828         ARG_INFO_LIT_hl
 829     },
 830     {
 831         0xff,
 832         0xeb,
 833         DA_LIT_ex | OPCODE_TYPE_LIT,
 834         ARG_INFO_LIT_de,
 835         ARG_INFO_LIT_hl
 836     },
 837     {
 838         0xff,
 839         0xcb,
 840         TABLE_CB | OPCODE_TYPE_SUB,
 841         ARG_INFO_NONE,
 842         ARG_INFO_NONE
 843     },
 844     {
 845         0xff,
 846         0xed,
 847         TABLE_ED | OPCODE_TYPE_SUB,
 848         ARG_INFO_NONE,
 849         ARG_INFO_NONE
 850     },
 851     {
 852         0xfd,
 853         0xfd,
 854         0 | OPCODE_TYPE_SUB,
 855         ARG_INFO_NONE,
 856         ARG_INFO_NONE
 857     },
 858     {
 859         0x00,
 860         0x00,
 861         DA_LIT_Q | OPCODE_TYPE_LIT,
 862         ARG_INFO_NONE,
 863         ARG_INFO_NONE
 864     }
 865 };
 866 
 867 static const struct InstructionInfo InstructionInfoTableCB[] =
 868 {
 869     // CB
 870     {
 871         0xc0,
 872         0x00,
 873         OPCODE_BUILD_RLC | OPCODE_TYPE_BUILD,
 874         ARG_INFO_MASK_07_R,
 875         ARG_INFO_NONE
 876     },
 877     {
 878         0x00,
 879         0x00,
 880         OPCODE_MASKABLE_BIT | OPCODE_TYPE_ARR,
 881         ARG_INFO_bit,
 882         ARG_INFO_MASK_07_R
 883     },
 884     {
 885         0x00,
 886         0x00,
 887         DA_LIT_Q | OPCODE_TYPE_LIT,
 888         ARG_INFO_NONE,
 889         ARG_INFO_NONE
 890     }
 891 };
 892 
 893 static const struct InstructionInfo InstructionInfoTableED[] =
 894 {
 895     // ED
 896     {
 897         0xc6,
 898         0x40,
 899         OPCODE_MASKABLE_INOUT | OPCODE_TYPE_ARR,
 900         ARG_INFO_MASK_38_R | ARG_TYPE_SWAPPABLE, // TODO swap on 0x01
 901         ARG_INFO_LIT_c | ARG_TYPE_CONTENTS
 902     },
 903     {
 904         0xc7,
 905         0x42,
 906         OPCODE_MASKABLE_SBC | OPCODE_TYPE_ARR,
 907         ARG_INFO_LIT_hl,
 908         ARG_INFO_MASK_30_RRS
 909     },
 910     {
 911         0xc7,
 912         0x43,
 913         DA_LIT_ld | OPCODE_TYPE_LIT,
 914         ARG_INFO_imm16 | ARG_TYPE_CONTENTS | ARG_TYPE_SWAPPABLE, // TODO swap in 0x08
 915         ARG_INFO_MASK_30_RRS
 916     },
 917     {
 918         0xc7,
 919         0x44,
 920         DA_LIT_neg | OPCODE_TYPE_LIT,
 921         ARG_INFO_NONE,
 922         ARG_INFO_NONE
 923     },
 924     {
 925         0xff,
 926         0x4d,
 927         DA_LIT_reti | OPCODE_TYPE_LIT,
 928         ARG_INFO_NONE,
 929         ARG_INFO_NONE
 930     },
 931     {
 932         0xc7,
 933         0x45,
 934         DA_LIT_retn | OPCODE_TYPE_LIT,
 935         ARG_INFO_NONE,
 936         ARG_INFO_NONE
 937     },
 938     {
 939         0xe7,
 940         0x47,
 941         DA_LIT_ld | OPCODE_TYPE_LIT,
 942         ARG_INFO_MASK_08_IR | ARG_TYPE_SWAPPABLE, // TODO swap not working -- on bit 4 0x10
 943         ARG_INFO_LIT_a
 944     },
 945     {
 946         0xf7,
 947         0x67,
 948         OPCODE_BUILD_RRD | OPCODE_TYPE_BUILD,
 949         ARG_INFO_NONE,
 950         ARG_INFO_NONE
 951     },
 952     {
 953         0xc7,
 954         0x46,
 955         DA_LIT_im | OPCODE_TYPE_LIT,
 956         ARG_INFO_im,
 957         ARG_INFO_NONE
 958     },
 959     {
 960         0xe4,
 961         0xa0,
 962         OPCODE_BUILD_LDI | OPCODE_TYPE_BUILD,
 963         ARG_INFO_NONE,
 964         ARG_INFO_NONE
 965     },
 966     {
 967         0x00,
 968         0x00,
 969         DA_LIT_Q | OPCODE_TYPE_LIT,
 970         ARG_INFO_NONE,
 971         ARG_INFO_NONE
 972     }
 973 };
 974 
 975 // sync with InstructionTableIndices
 976 static const struct InstructionInfo* InstructionInfoTableArray[TABLE_COUNT] =
 977 {
 978     InstructionInfoTableMain_00,
 979     InstructionInfoTableMain_40,
 980     InstructionInfoTableMain_80,
 981     InstructionInfoTableMain_c0,
 982     InstructionInfoTableCB,
 983     InstructionInfoTableED
 984 };
 985 
 986 uint8_t shiftMaskToByte(uint8_t b, uint8_t shiftMaskByte)
 987 {
 988     return (b >> (shiftMaskByte >> 4)) & shiftMaskByte & 0x0f;
 989 }
 990 
 991 static const char IM_0Q12[4] = { '0', '?', '1', '2' };
 992 static const char* const FORMAT1C = "%c";
 993 static const char* const FORMAT1 = "%01xh";
 994 static const char* const FORMAT2 = "%02xh";
 995 static const char* const FORMAT4 = "%04xh";
 996 static const char* const FORMAT_CONTENTS = "(%s)";
 997 
 998 uint8_t* disassemble(uint8_t* loc, char* line)
 999 {
1000     uint8_t b; // instruction byte being disassembled
1001     uint8_t table = 0;
1002     const struct InstructionInfo* entry;
1003     bool swap = false;
1004     uint8_t argCount = 0;
1005     char arg0[8];
1006     char arg1[8];
1007     char* args[2] = { arg0, arg1 };
1008     uint8_t opcodeInfo;
1009     uint8_t opcodeIndex;
1010     uint16_t offset;
1011     uint8_t hl_ix_iy = 0;
1012     char offsetStr[6] = { 0 };
1013 
1014     *line = 0;
1015     b = *loc++;
1016     table = b >> 6;
1017 
1018     // See if we need a special table
1019     // 1100 1011 cb
1020     // 1110 1101 ed
1021     // 11-0 1--1
1022     // 1101 1101
1023     // 1111 1101
1024     // 11-1 1101
1025     if ((b & 0xdf) == 0xdd)
1026     {
1027         if (b == 0xdd)
1028         {
1029             b = *loc++;
1030             table = b >> 6;
1031             hl_ix_iy = 1;
1032         }
1033         else if (b == 0xfd)
1034         {
1035             b = *loc++;
1036             table = b >> 6;
1037             hl_ix_iy = 2;
1038         }
1039     }
1040     if ((b & 0xd9) == 0xc9)
1041     {
1042         if (b == 0xcb)
1043         {
1044             b = *loc++;
1045             table = TABLE_CB;
1046         }
1047         else if (b == 0xed)
1048         {
1049             b = *loc++;
1050             table = TABLE_ED;
1051         }
1052     }
1053 
1054     entry = InstructionInfoTableArray[table];
1055     while (entry->mask != 0)
1056     {
1057         uint8_t opcodeType;
1058         if ((b & entry->mask) == entry->value)
1059         {
1060             break;
1061         }
1062         entry++;
1063     }
1064 
1065     // got here so we found something to process
1066     opcodeInfo = entry->opcodeInfo;
1067     opcodeIndex = entry->opcodeInfo & 0x3f;
1068     if ((opcodeInfo & 0x80) == 0)
1069     {
1070         if ((opcodeInfo & 0x40) == 0)
1071         {
1072             // OPCODE_TYPE_LIT
1073             strcpy(line, LiteralStringArray[opcodeIndex]);
1074         }
1075         else
1076         {
1077             // OPCODE_TYPE_ARR
1078             const struct ShiftMaskAndIndexStartInfo* opcodeByMaskInfo = &OpcodeByMaskShiftMaskArray[opcodeIndex];
1079             uint8_t index = opcodeByMaskInfo->indexStart + shiftMaskToByte(b, opcodeByMaskInfo->shiftMaskInfo);
1080             strcpy(line, LiteralStringArray[OpcodeByMaskArray[index]]);
1081         }
1082     }
1083     else
1084     {
1085         // OPCODE_TYPE_BIT
1086         buildOpcode(b, opcodeIndex, line);
1087     }
1088 
1089     for(argCount = 0; argCount < 2; argCount++)
1090     {
1091         uint8_t argInfo = (&entry->argInfoIndex0)[argCount];
1092         char buffer[8];
1093         const char* argText;
1094         char* arg = args[argCount];
1095         uint16_t argData;
1096         const char* format = NULL;
1097         uint8_t lit = 0xff;
1098         bool contents = false;
1099 
1100         // no more arguments
1101         if (argInfo == 0)
1102         {
1103             break;
1104         }
1105 
1106         // extra info --swappable/contents
1107         if ( ((argInfo & ARG_TYPE_SWAPPABLE) != 0) && !swap)
1108         {
1109             if (table < 4)
1110             {
1111                 swap = (b & 0x08) != 0;
1112             }
1113             else if (table == TABLE_ED)
1114             {
1115                 uint8_t swapMask;
1116                 // entryMask bit
1117                 //   c6       0/0x01
1118                 //   c7       3/0x08
1119                 //   e7       4/0x10
1120                 if ((entry->mask & 0x20) == 0)
1121                 {
1122                     if ((entry->mask & 0x01) == 0)
1123                     {
1124                         swapMask = 0x01;
1125                     }
1126                     else
1127                     {
1128                         swapMask = 0x08;
1129                     }
1130                 }
1131                 else
1132                 {
1133                     swapMask = 0x10;
1134                 }
1135                 swap = (b & swapMask) != 0;
1136             }
1137         }
1138         contents = (argInfo & ARG_TYPE_CONTENTS) != 0;
1139 
1140         argInfo &= 0x3f; // remove swap/contents bits
1141         // either set lit or argText
1142         if (argInfo < ARG_TYPE_LIT)
1143         {
1144             // Specials
1145             switch (argInfo & 0x07)
1146             {
1147             case ARG_INFO_rel:
1148                 argData = (uint16_t)(loc - 1) + (int8_t)(*loc);
1149                 loc++;
1150                 format = FORMAT4;
1151                 break;
1152             case ARG_INFO_imm8:
1153                 argData = (uint8_t)(*loc);
1154                 loc++;
1155                 format = FORMAT2;
1156                 break;
1157             case ARG_INFO_imm16:
1158                 argData = *(uint16_t*)loc;
1159                 loc += 2;
1160                 format = FORMAT4;
1161                 break;
1162             case ARG_INFO_bit:
1163                 argData = (b >> 3) & 0x07;
1164                 format = FORMAT1;
1165                 break;
1166             case ARG_INFO_rst:
1167                 argData = (b & 0x38);
1168                 format = FORMAT2;
1169                 break;
1170             case ARG_INFO_im:
1171                 argData = IM_0Q12[(b & 0x18) >> 3];
1172                 format = FORMAT1C;
1173                 break;
1174             }
1175             sprintf(buffer, format, argData);
1176             argText = &buffer[0];
1177         }
1178         else if (argInfo < ARG_TYPE_MASK)
1179         {
1180             // Lit
1181             lit = ArgByLitIndexToStringLiteralIndex[argInfo & 0x0f];
1182         }
1183         else
1184         {
1185             // mask
1186             const struct ShiftMaskAndIndexStartInfo* maskInfo = &ArgShiftMaskStartIndex[argInfo & 0x0f];
1187             //printf("MASKINGO: %02x b: %02x -> %d\r\n", maskInfo->shiftMaskInfo, b, shiftMaskToByte(b, maskInfo->shiftMaskInfo));
1188             lit = ArgByMaskArray[maskInfo->indexStart + shiftMaskToByte(b, maskInfo->shiftMaskInfo)];
1189         }
1190 
1191         // indexed lit might have the contents flag set
1192         if ((lit != 0xff) && ((lit & ARG_TYPE_CONTENTS) != 0))
1193         {
1194             lit &= 0x3f;
1195             contents = true;
1196         }
1197 
1198         // Convert DD/FD, hl to ix/iy and (hl) to (ix/iy+(int8_t)d)
1199         if ((hl_ix_iy > 0) && (lit == DA_LIT_hl))
1200         {
1201             if (!contents || (table < 4 && b == 0xe9))
1202             {
1203                 lit = (DA_LIT_hl + hl_ix_iy);
1204             }
1205             else
1206             {
1207                 offset = (int16_t)*(int8_t*)loc++;
1208                 sprintf(buffer, "%s%c%02x", LiteralStringArray[DA_LIT_hl + hl_ix_iy], (offset < 0) ? '-' : '+', abs(offset));
1209                 argText = &buffer[0];
1210                 lit = 0xff; // switch lit out and argText in
1211             }
1212         }
1213 
1214         if (lit != 0xff)
1215         {
1216             argText = LiteralStringArray[lit];
1217         }
1218 
1219         if (contents)
1220         {
1221             sprintf(arg, "(%s)", argText);
1222         }
1223         else
1224         {
1225             strcpy(arg, argText);
1226         }
1227 
1228         argInfo >>= 4;
1229     }
1230     if (swap)
1231     {
1232         args[0] = arg1;
1233         args[1] = arg0;
1234     }
1235     if (argCount > 0)
1236     {
1237         strcat(line, " ");
1238         strcat(line, args[0]);
1239     }
1240     if (argCount > 1)
1241     {
1242         strcat(line, ", ");
1243         line = strcat(line, args[1]);
1244     }
1245     return loc;
1246 }

Breakpoints Starting to Work

Mon, 19 Oct 2015 12:43:00 -0700

I’m finally getting breakpoints to start working!

RST 20H (0xe7) is what I use to generate breakpoints. Since the code copies itself to RAM banks and executes from RAM, the breakpoint code can swap in e7 for whatever instruction is at a certain point. This causes the execution to run off to 0x0020.

Once there, it pushes all registers. It also pushes sp (i.e. ld hl, 0; add hl, sp; push hl) and then calls a function that loads hl with a pointer to a function and jumps to it. The default function just returns. But if the pointer is modified, execution can go someplace else.

And that place is bpBreak.

The bpBreak function handles loading a pointer to the registers contents struct over the stack where the the registers are stored. That struct pointer can be used to display and change register contents. It then it replaces all the RST 20H opcodes with the original contents. While doing that, it updates the breakpoint ignore counter, deletes delete-on-break breakpoints, and deletes break-on-hit breakpoints if the pc is where the break occurred. Finally, if any breakpoint had a count of 0, it will start the break prompt, otherwise skip straight to continuing.

The break prompt is where user can interactively set, delete, and change breakpoints, view and change register contents, and view and change memory.

Step is done with temporary breakpoints that delete on break. A breakpoint usually goes at the beginning of the next instruction. The exceptions are ret, jp, and jr instructions since execution never gets beyond. Except, of course, when they are conditional. In that case, the breakpoint must be set at the destination of the jump. There are 6 possibilities of which I deal with 4; call, jp: place breakpoint at (uint16_t)(bpRegs->pc+1) jr: place breakpoint at pc+(uint8_t)(bpRegs->pc+1) ret: place breakpoint at (uint16_t)(bpRegs->sp) jp (hl): place breakpoint at bpRegs->hl rst: this is not done but one could place breakpoints at 00, 08, 10, 18, 20, 28, 30, or 38 halt: this is not done but one could place a breakpoint at 66

Next is like step except if there is a call (i.e. breakpoint uses absolute addressing, may reach next instruction, and is not conditional), then the breakpoint is not placed at the destination. This fails to take into account that calls can be conditional, but the SDCC compiler is not generating conditional calls, at least at the optimization level I’m using.

Continue is a little tricky. It is assumed that the current instruction is a breakpoint. If it isn’t this is overkill, but if it is, we can’t just load the breakpoints and run–we’d break at the same point again. Rather, the breakpoint has be temporarily disabled, a step has to take place, and the breakpoint must be restored once past it. This is done by never loading any breakpoint at the current pc, and having the code that unloads the breakpoint determine if a break is necessary. If a deletion-break breakpoint is hit and has an ignore count greater than 0, it will not generate a break.

Here are two breakpoint files. The first is the basic breakpoint function:

  1 // __asm__("rst 20h") == 0xe7
  2 #define RST_20H ((uint8_t)(0xe7))
  3 
  4 struct Regs* bpRegs;
  5 struct BP bpInfo[BREAKPOINT_COUNT];
  6 
  7 
  8 // declare fnRST_20H for telling bank 0 how to get to bpBreak
  9 extern void(*fnRST_20H)();
 10 
 11 // Initialize breakpoint system
 12 void bpInit()
 13 {
 14     memset(bpInfo, 0, sizeof(bpInfo));
 15     fnRST_20H = bpBreak;
 16 }
 17 
 18 // crt1 calls this instead of main. This calls main
 19 void bpStart(void(*initBP)())
 20 {
 21     bpSet((uint8_t*)initBP, (1 << BP_FLAG_ENABLED) | (1 << BP_FLAG_DELETE_ON_HIT), 0);
 22     bpLoadBreakPoints(NULL);
 23 }
 24 
 25 // Sets a breakpoint at location with behavior flags and an ignore count
 26 uint8_t bpSet(uint8_t* location, uint8_t flags, uint8_t count)
 27 {
 28     uint8_t bp;
 29 
 30     // get unusued and look for same
 31     for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
 32     {
 33         struct BP* b = &bpInfo[bp];
 34         if ((b->flags & (1 << BP_FLAG_ASSIGNED)) == 0)
 35         {
 36             b->flags |= (1 << BP_FLAG_ASSIGNED);
 37             break;
 38         }
 39         else if (b->addr == location)
 40         {
 41             if (((b->flags ^ flags) & ~0x03) == 0)
 42             {
 43                 // such a breakpoint already exists
 44                 return bp;
 45             }
 46         }
 47     }
 48 
 49     // Set the breakpoint
 50     if (bp < BREAKPOINT_COUNT)
 51     {
 52         struct BP* b = &bpInfo[bp];
 53         b->flags = flags | (1 << BP_FLAG_ASSIGNED);
 54         b->addr = location;
 55         b->count = count;
 56         printf("Set BP%x @ %p (%x-%d)\r\n", bp, location, flags, count);
 57     }
 58     return bp;
 59 }
 60 
 61 // Delete a breakpoint
 62 void bpUnset(uint8_t bp)
 63 {
 64     struct BP* b = &bpInfo[bp];
 65     b->flags = 0x00;
 66     printf("Unset BP%x @ %p (%x-%d)\r\n", bp, b->addr, b->flags, b->count);
 67 }
 68 
 69 // Enable or disable a breakpoint
 70 void bpEnable(uint8_t bp, bool enable)
 71 {
 72     if (enable)
 73     {
 74         bpInfo[bp].flags |= (1 << BP_FLAG_ENABLED);
 75         bpInfo[bp].count = 0;
 76     }
 77     else
 78     {
 79         bpInfo[bp].flags &= ~(1 << BP_FLAG_ENABLED);
 80     }
 81 }
 82 
 83 // Find if a breakpoint is enabled
 84 bool bpIsEnabled(uint8_t bp)
 85 {
 86     return (bpInfo[bp].flags & (1 << BP_FLAG_ENABLED)) != 0;
 87 }
 88 
 89 // Gets the first breakpoint at addr of 0xff
 90 uint8_t bpAt(uint8_t* addr)
 91 {
 92     uint8_t bp;
 93     for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
 94     {
 95         if (bpInfo[bp].addr == addr)
 96         {
 97             return bp;
 98         }
 99     }
100     return 0xff;
101 }
102 
103 // Swaps in the RST 20H into the locations with breakpoints
104 // Breakpoints are not swapped at 'pc'
105 void bpLoadBreakPoints(uint8_t* pc)
106 {
107     uint8_t bp = 0;
108     for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
109     {
110         struct BP* b = &bpInfo[bp];
111         if ((b->flags & 0x03) == 0x03 && b->addr != pc) // assigned and enabled and not at PC
112         {
113             uint8_t swap = *(b->addr);
114             if (swap == RST_20H)
115             {
116                 // already a breakpoint there
117             }
118             else
119             {
120                 b->swap = swap;
121                 *(b->addr) = RST_20H;
122                 printf("RST 20 to %02x @ %p\r\n", b->swap, b->addr);
123             }
124         }
125     }
126 }
127 
128 // Restores RST 20H with the original opcodes
129 // decrements ignore count for breakpoints who addr is 'pc'
130 // Returns whether any breakpoints at 'pc' were hit and had an ignore count of 0
131 bool bpUnloadBreakPoints(uint8_t* pc)
132 {
133     uint8_t bp = 0;
134     bool doBreak = false;
135     for (bp = 0; bp < BREAKPOINT_COUNT; bp++)
136     {
137         struct BP* b = &bpInfo[bp];
138         if ((b->flags & (1 << BP_FLAG_ASSIGNED)) != 0)
139         {
140             if ((b->flags & (1 << BP_FLAG_ENABLED)) != 0)
141             {
142                 uint8_t swap = *(b->addr);
143                 if (swap == RST_20H)
144                 {
145                     printf("RST 20 from %02x @ %p\r\n", b->swap, b->addr);
146                     *(b->addr) = b->swap;
147                 }
148                 if (b->addr == pc)
149                 {
150                     if ((b->count > 0))
151                     {
152                         b->count--;
153                     }
154                     else
155                     {
156                         doBreak = true;
157                     }
158 
159                     // delete on hit
160                     if ((b->flags & (1 << BP_FLAG_DELETE_ON_HIT)) != 0)
161                     {
162                         b->flags = 0;
163                     }
164                 }
165             }
166             // delete on break BP
167             if ((b->flags & (1 << BP_FLAG_DELETE_ON_BREAK)) != 0)
168             {
169                 b->flags = 0;
170             }
171         }
172     }
173     return doBreak;
174 }
175 
176 // This set breakpoints for certain types: 0-step 1-next 2-continue
177 // Step/Next: if !BRANCH_NO_STEP set bp @ pc+il
178 // Step: if BRANCH_ABS set @ (pc+1)
179 // Step: if BRANCH_REL set @ pc + (pc+1)
180 // Step: if BRANCH_RET set @ (sp-2)
181 // Step: if BRANCH_HL set @ hl
182 void bpStep(uint8_t type)
183 {
184     uint8_t* pc;
185     uint8_t branchInfo;
186     uint8_t instrLen;
187     bool breakOnNextInstr;
188     bool breakOnDest;
189     uint8_t count;
190     uint8_t nextFlags;
191 
192     // get PC
193     pc = (uint8_t*)bpRegs->pc;
194 
195     // get next instruction address
196     instrLen = z80InstructionLength(pc);
197     branchInfo = instrLen & 0xf8;
198     instrLen = instrLen & 0x07;
199 
200     printf("branch %02x\r\n", branchInfo);
201 
202     // figure out what to do
203     // if not branching away permanently, set a breakpoint there
204     breakOnNextInstr = (branchInfo & BRANCH_ALWAYS) == 0;
205 
206     // count is 0 unless type is continue
207     // If count is 1, will not return to break point prompt--will just continue
208     count = (type == 2) ? 1 : 0;
209 
210     // How flags work
211     // step: delete on hit for next and delete on break dest
212     // next: delete on hit for next
213     // continue: always delete on any break--restart immediately
214     nextFlags = (type == 2) ? (1 << BP_FLAG_DELETE_ON_BREAK) : (1 << BP_FLAG_DELETE_ON_HIT);
215     nextFlags |= (1 << BP_FLAG_ENABLED);
216     //nextFlags = (1 << BP_FLAG_DELETE_ON_BREAK) | (1 << BP_FLAG_ENABLED);
217 
218     // place breakpoint if not NO_STEP branch (jp **, jp (hl), ret/i/n, jr)
219     if (breakOnNextInstr)
220     {
221         bpSet(pc + instrLen, nextFlags, count);
222     }
223 
224     // BP on branch destination
225     breakOnDest = ((branchInfo & 0xf8) != 0);
226     if ((type == 1) && ((branchInfo & BRANCH_CALL) != 0))
227     {
228         breakOnDest = false; // if user is using 'next' on a call
229     }
230 
231     if (breakOnDest)
232     {
233         uint8_t branchType = branchInfo & 0x30;
234         uint16_t target = 0;
235         // get branch addr (rel, abs, (hl), (sp-2)
236         if (branchType == BRANCH_ABS)
237         {
238             target = *(uint16_t*)(pc + 1);
239         }
240         else if (branchType == BRANCH_REL)
241         {
242             target = (uint16_t)pc + (int8_t)(pc[1]);
243         }
244         else if (branchType == BRANCH_RET)
245         {
246             target = *(uint16_t*)(bpRegs->sp);
247         }
248         else// if (branchType == BRANCH_HL)
249         {
250             target = bpRegs->hl;
251         }
252 
253         // place breakpoint
254         bpSet((uint8_t*)target, (1 << BP_FLAG_DELETE_ON_BREAK) | (1 << BP_FLAG_ENABLED), count);
255     }
256 }
257 
258 // RST 20H calls this after 
259 void bpBreak() __naked
260 {
261     //RST_20H all registers pushed
262     __asm__("di");
263     __asm__("ld hl, #2");
264     __asm__("add hl, sp");
265     __asm__("push hl");
266     __asm__("ld (_bpRegs), hl");
267     __asm__("call _bpPrompt");
268     __asm__("pop hl ; toss");
269     __asm__("ret");
270 }

This file snippet is for breakpoint prompt features:

  1 struct BpCmd {
  2     const char* cmd;
  3     const char* desc;
  4     uint8_t(*fn)(const char* line);
  5 };
  6 
  7 void showMem(uint16_t address, uint16_t length)
  8 {
  9     uint8_t i;
 10     char* ph;
 11     char* pa;
 12     char line[75];
 13     w_bb shift;
 14     address = address & 0xfff0;
 15     length = (length + 15) & 0xfff0;
 16     memset(line, ' ', sizeof(line) - 1);
 17     line[sizeof(line) - 1] = 0;
 18     line[4] = ':';
 19     while (length)
 20     {
 21         shift.uw = address;
 22         ph = &line[0];
 23         pa = &line[4 + 1 + 1 + 1 + 16 * 3 + 1];
 24         *ph++ = __ascii[shift.ubb.h >> 4];
 25         *ph++ = __ascii[shift.ubb.h & 0x0f];
 26         *ph++ = __ascii[shift.ubb.l >> 4];
 27         *ph++ = __ascii[shift.ubb.l & 0x0f];
 28         ph++;
 29         ph++;
 30         // 16 bytes
 31         for (i = 0; i < 16; i++)
 32         {
 33             uint8_t b;
 34             b = *(char*)(address + i);
 35             *ph++ = __ascii[b >> 4];
 36             *ph++ = __ascii[b & 0x0f];
 37             ph++;
 38 
 39             // unprintables to .
 40             if (b < ' ' || b > 0x7e)
 41             {
 42                 b = '.';
 43             }
 44             *pa++ = b;
 45 
 46             // gap
 47             if (i == 7)
 48             {
 49                 ph++;
 50                 pa++;
 51             }
 52 
 53         }
 54         puts(line);
 55         address += 16;
 56         length -= 16;
 57     }
 58 }
 59 
 60 static void showRegs()
 61 {
 62     printf("af: %04x  bc: %04x  de: %04x  hl=%04x\r\n", bpRegs->af, bpRegs->bc, bpRegs->de, bpRegs->hl);
 63     printf("pc: %04x  sp: %04x  ix: %04x  iy=%04x\r\n", bpRegs->pc, bpRegs->sp, bpRegs->ix, bpRegs->iy);
 64 }
 65 
 66 static void showBreakpoint(uint8_t bp)
 67 {
 68     struct BP* b = &bpInfo[bp];
 69     printf("%x: addr=%04x en=%x count=%02x\r\n", bp, b->addr, (b->flags & (1 << BP_FLAG_ENABLED)) != 0, b->count);
 70 }
 71 static void showBreakpoints()
 72 {
 73     uint8_t i;
 74     for (i = 0; i < BREAKPOINT_COUNT; i++)
 75     {
 76         struct BP* b = &bpInfo[i];
 77         if ((b->flags & (1 << BP_FLAG_ASSIGNED)) != 0)
 78         {
 79             showBreakpoint(i);
 80         }
 81     }
 82 }
 83 
 84 static const struct BpCmd commands[] =
 85 {
 86     {
 87         "?",
 88         "list",
 89         bpIntHelp
 90     },
 91     {
 92         "l",
 93         "list bp's",
 94         bpIntList
 95     },
 96     {
 97         "s",
 98         "step",
 99         bpIntStep
100     },
101     {
102         "n",
103         "next",
104         bpIntNext
105     },
106     {
107         "c",
108         "continue",
109         bpIntContinue
110     },
111     {
112         "b",
113         "set bp @ addr",
114         bpIntCreate
115     },
116     {
117         "d",
118         "delete bp # or all",
119         bpIntDelete
120     },
121     {
122         "t",
123         "toggle bp",
124         bpIntToggle
125     },
126     {
127         "r",
128         "see regs or set rr v",
129         bpIntRegs
130     },
131     {
132         "m",
133         "see RAM",
134         bpIntMem
135     },
136 };
137 
138 const static uint8_t commandLength = sizeof(commands) / sizeof(commands[0]);
139 
140 
141 static uint8_t bpIntList(const char* line)
142 {
143     line; // suppress warning
144     showBreakpoints();
145     return 0;
146 }
147 
148 static uint8_t bpIntHelp(const char* line)
149 {
150     uint8_t i;
151     line; // suppress warning
152     for (i = 0; i < commandLength; i++)
153     {
154         printf("%s - %s\r\n", commands[i].cmd, commands[i].desc);
155     }
156     return 0;
157 }
158 
159 static uint8_t bpIntContinue(const char* line)
160 {
161     line; // suppress warning
162     bpStep(2);
163     return 0xff; // continue
164 }
165 
166 static uint8_t bpIntStep(const char* line)
167 {
168     line; // suppress warning
169     bpStep(0);
170     return 0xff; // continue
171 }
172 
173 static uint8_t bpIntNext(const char* line)
174 {
175     line; // suppress warning
176     bpStep(1);
177     return 0xff; // continue
178 }
179 
180 static uint8_t bpIntCreate(const char* line)
181 {
182     if (*line++ == ' ')
183     {
184         uint16_t addr = extractHex(&line);
185         uint8_t count = 0;
186         if (*line == ' ')
187         {
188             line++;
189             count = extractHex(&line);
190         }
191         if (*line == 0)
192         {
193             uint8_t i = bpSet((uint8_t*)addr, (1<<BP_FLAG_ENABLED), count);
194             if (i == 0xff)
195             {
196                 puts("BP full");
197                 return 1;
198             }
199             else
200             {
201                 showBreakpoint(i);
202             }
203         }
204         else
205         {
206             return 2;
207         }
208     }
209     else
210     {
211         return 3;
212     }
213     return 0;
214 }
215 
216 static uint8_t bpIntDelete(const char* line)
217 {
218     uint8_t status = 0;
219     if (*line == ' ')
220     {
221         uint8_t i;
222         line++;
223         i = extractHex(&line);
224         if (*line == 0 && i < BREAKPOINT_COUNT)
225         {
226             bpUnset(i);
227         }
228     }
229     return 0;
230 }
231 
232 static uint8_t bpIntToggle(const char* line)
233 {
234     //uint8_t status = 0;
235     uint8_t bp;
236     if (*line == ' ')
237     {
238         bp = extractHex(&line);
239     }
240     else if (*line == 0)
241     {
242         bp = bpAt((uint8_t*)bpRegs->pc);
243     }
244     else
245     {
246         return 1;
247     }
248     if (bp >= BREAKPOINT_COUNT)
249     {
250         return 2;
251     }
252     bpEnable(bp, !bpIsEnabled(bp));
253     showBreakpoint(bp);
254     return 0;
255 }
256 
257 static const char* const regs = "SPiyixhldebcafpc";
258 
259 static uint8_t bpIntRegs(const char* line)
260 {
261     //uint8_t status = 0;
262     if (*line == 0)
263     {
264         showRegs();
265         return 0;
266     }
267     else if (*line == ' ')
268     {
269         uint8_t i;
270         uint16_t search;
271         const uint16_t* reg = (const uint16_t*)regs;
272 
273         line++;
274         search = *(uint16_t*)line;
275 
276         for (i = 0; i < 7; i++)
277         {
278             if (search == *reg)
279             {
280                 uint16_t val;
281                 line += 3;
282                 val = extractHex(&line);
283                 if (*line == 0)
284                 {
285                     ((uint16_t*)bpRegs)[i] = val;
286                     showRegs();
287                 }
288                 else
289                 {
290                     puts("?");
291                 }
292             }
293             reg++;
294         }
295     }
296     return 0;
297 }
298 
299 static uint8_t bpIntMem(const char* line)
300 {
301     uint16_t addr = 0;
302     uint16_t len = 16;
303     if (*line++ == ' ')
304     {
305         addr = extractHex(&line);
306         if (*line++ == ' ')
307         {
308             len = extractHex(&line);
309         }
310         if (*line == 0)
311         {
312             showMem(addr, len);
313             return 0;
314         }
315     }
316     return 1;
317 }
318 
319 // do prompt for breaks
320 //  ?           list commands
321 //  l           list breakpoints
322 //  c           continue
323 //  s           step
324 //  n           next
325 //  b xxxx (cc) break @ xxxx (optional countdown)
326 //  d ##        delete ##
327 //  t ##        toggle ## enable
328 //  r           show regs
329 //  r rr xxxx   set reg (except sp)
330 //  m xxxx xxxx show mem
331 void bpPrompt()
332 {
333     char buffer[32];
334     char* p;
335     uint8_t i;
336     uint16_t pc = bpRegs->pc - 1; // source of RST_20
337     uint8_t interruptSave;
338     bool doBreak;
339 
340     bpRegs->pc = pc; // restore to the instruction that was supposed to be there
341     doBreak = bpUnloadBreakPoints((uint8_t*)pc);
342     interruptSave = ei_save();
343 
344     while (doBreak)
345     {
346         uint8_t result = 0;
347         char c;
348         printf("(brk @ %p)> ", pc);
349         gets(buffer);
350         p = &buffer[0];
351         c = *p;
352         for (i = 0; i < commandLength; i++)
353         {
354             const char* cmd = commands[i].cmd;
355             uint8_t len = strlen(cmd);
356             if (strncmp(commands[i].cmd, p, len) == 0)
357             {
358                 result = commands[i].fn(&p[len]);
359             }
360         }
361 
362         if (result == 0xff)
363         {
364             break;
365         }
366         else if (result != 0)
367         {
368             printf("error %d\r\n", result);
369         }
370     }
371     bpLoadBreakPoints((uint8_t*)pc);
372     di_restore(interruptSave);
373 }

This is the part of interrupt.c that is relevant:

 1 static void ret() __naked
 2 {
 3     __asm__("ret");
 4 }
 5 // This is preset to 'ret' If the code runs frojmj flash, this is necessary.
 6 // If the code runs from RAM, this can be overridden.
 7 void(*fnRST_20H)() = ret;
 8 static void call_hl() __naked
 9 {
10     __asm__("jp (hl)");
11 }
12 void do_RST_20H() __naked
13 {
14     __asm__("push af");
15     __asm__("push bc");
16     __asm__("push de");
17     __asm__("push hl");
18     __asm__("push ix");
19     __asm__("push iy");
20     // push sp
21     __asm__("ld hl, #14");
22     __asm__("add hl, sp");
23     __asm__("push hl");
24 
25     __asm__("ld hl, (_fnRST_20H)");
26     __asm__("call _call_hl");
27 
28     __asm__("pop iy"); //  toss  SP
29     __asm__("pop iy");
30     __asm__("pop ix");
31     __asm__("pop hl");
32     __asm__("pop de");
33     __asm__("pop bc");
34     __asm__("pop af");
35     __asm__("ret");
36 }

Z-80 Instruction Lengths

Mon, 19 Oct 2015 12:21:00 -0700

In order to handle breakpoints functionality of step, next, and continue, it is necessary to know 1) how long the current instruction is and 2) whether and how it branches.

So I coded up a quick function that takes a pointer to a location and returns 1) 1-4 in the lower 3 bits with instruction length, 2 bits with the branch type (absolute, relative, return, and jp (hl)), one bit to indicate the branch is conditional, and one bit for instructions that always branch away and will never get to the next instruction.

Note that the ‘rst’ and ‘halt’ commands don’t have branch information. Anyone wanting to try to use this code will want to add that if they need it.

Here it is:

  1 // The following are found in pBranchInfo
  2 #define BRANCH_CALL     (0x08)
  3 // relative to pc + (int8_t)(opcode+1) ALWAYS or COND
  4 #define BRANCH_REL      (0x20)
  5 // absolute to (void*)(opcode+1) ALWAYS or COND
  6 #define BRANCH_ABS      (0x10)
  7 // return to (void*)(sp-2) ALWAYS or COND
  8 #define BRANCH_RET      (0x30)
  9 // to (hl) // ALWAYS but never COND
 10 #define BRANCH_HL       (0x00)
 11 // conditional--bp necessary after instruction
 12 #define BRANCH_COND     (0x40)
 13 // always--will never got to pc+length--certain to branch
 14 #define BRANCH_ALWAYS   (0x80)
 15 
 16 
 17 struct InstLen
 18 {
 19     uint8_t mask;
 20     uint8_t value;
 21     uint8_t data;
 22 };
 23 
 24 static const struct InstLen scan00[] =
 25 {
 26     // ld rr, **
 27     {
 28         0xcf, 0x01, 3
 29     },
 30     // ld (hl)/a <-> **
 31     {
 32         0xe7, 0x22, 3
 33     },
 34     // ld r, *
 35     {
 36         0xc7, 0x06, 2
 37     },
 38     // jr f, *
 39     {
 40         0xe7, 0x20, 2 | BRANCH_REL | BRANCH_COND
 41     },
 42     // djnz *
 43     {
 44         0xff, 0x10, 2 | BRANCH_REL | BRANCH_COND
 45     },
 46     // jr *
 47     {
 48         0xff, 0x18, 2 | BRANCH_REL | BRANCH_ALWAYS
 49     },
 50 };
 51 
 52 static const struct InstLen scan11[] =
 53 {
 54     // ret f (not detault b/c branch)
 55     {
 56         0xc7, 0xc0, 1 | BRANCH_RET | BRANCH_COND
 57     },
 58     // ret (not detault b/c branch)
 59     {
 60         0xff, 0xc9, 1 | BRANCH_RET | BRANCH_ALWAYS
 61     },
 62     // jp (hl)
 63     {
 64         0xff, 0xe9, 1 | BRANCH_HL | BRANCH_ALWAYS
 65     },
 66     // jp f, **
 67     {
 68         0xc7, 0xc2, 3 | BRANCH_ABS | BRANCH_COND
 69     },
 70     // call f, **
 71     {
 72         0xc7, 0xc4, 3 | BRANCH_ABS | BRANCH_COND | BRANCH_CALL
 73     },
 74     // jp **
 75     {
 76         0xff, 0xc3, 3 | BRANCH_ABS | BRANCH_ALWAYS
 77     },
 78     // call **
 79     {
 80         0xff, 0xcd, 3 | BRANCH_ABS | BRANCH_CALL
 81     },
 82     // arith *, *
 83     {
 84         0xc7, 0xc6, 2
 85     },
 86     // out/in(*), a
 87     {
 88         0xf7, 0xd3, 2
 89     },
 90     // bit op
 91     {
 92         0xff, 0xcb, 2
 93     }
 94 };
 95 
 96 static const struct InstLen scanED[] =
 97 {
 98     // ld (rr) <-> **
 99     {
100         0xc7, 0x43, 4
101     }
102 };
103 
104 static const struct InstLen scanDDFD[] =
105 {
106     // ld ix, **
107     {
108         0xff, 0x21, 4
109     },
110     // ld ix <-> (**)
111     {
112         0xf7, 0x22, 4
113     },
114     // ld (ix+*), * order dep
115     {
116         0xff, 0x36, 4
117     },
118     // various
119     {
120         0x07, 0x06, 3
121     },
122     // ld (ix+*), r
123     {
124         0xb8, 0x30, 3
125     },
126     // bit ops
127     {
128         0xff, 0xcb, 3
129     },
130 };
131 
132 // Returns the length in the first 3 bits and the BRANCH_* bits in the upper 5 bits
133 uint8_t z80InstructionLength(uint8_t* start)
134 {
135     uint8_t opcode = *start++;
136     const struct InstLen* scanner;
137     int i;
138     uint8_t length;
139     uint8_t instructionLength = 1;
140 
141     if ((opcode & 0x80) == 0)
142     {
143         if ((opcode & 0x40) == 0)
144         {
145             scanner = scan00;
146             length = sizeof(scan00) / sizeof(scan00[0]);
147         }
148         else
149         {
150             return 1;
151         }
152     }
153     else
154     {
155         if ((opcode & 0x40) == 0)
156         {
157             return 1;
158         }
159         else
160         {
161             if ((opcode & 0xdf) == 0xdd)
162             {
163                 scanner = scanDDFD;
164                 length = sizeof(scanDDFD) / sizeof(scanDDFD[0]);
165                 instructionLength = 2;
166                 opcode = *start++;
167             }
168             else if (opcode == 0xed)
169             {
170                 scanner = scanED;
171                 length = sizeof(scanED) / sizeof(scanED[0]);
172                 instructionLength = 2;
173                 opcode = *start++;
174             }
175             else
176             {
177                 scanner = scan11;
178                 length = sizeof(scan11) / sizeof(scan11[0]);
179             }
180         }
181     }
182     for (i = 0; i < length; i++)
183     {
184         const struct InstLen* scan = &scanner[i];
185         if ((scan->mask & opcode) == scan->value)
186         {
187             instructionLength = scan->data;
188             break;
189         }
190     }
191     return instructionLength;
192 }

Update

Fri, 09 Oct 2015 11:49:00 -0700

I’ve been working on testing the vector which allows me to have library (C/driver) functions in bank 0 and separately compile a program in bank 1 that links to a vector that just forwards the calls from bank 1 to the right place in bank 0. I’ve found a few issues but for the most part it works as expected.

Also, I have coded but not yet started testing the breakpoint code. All it does now is create/delete/enable/disable breakpoints, show/set registers, and dump memory. Step and next require getting the size of the current instruction as well as the possible branch destination. So that’s still on the back burner.

Well, off to start testing the debug code….

Breakpoints

Sat, 03 Oct 2015 11:39:00 -0700

Debugging is hard. It would easier with breakpoints. But breakpoints need to be implemented. How?

Well, I can use a RST vector. Say RST 20H.

If I’m running from RAM, I can replace the first byte of all instructions at a break location with RST 20H and then start executing. Then when that’s called, go into breakpoint mode. In breakpoint mode, I need to make the following commands available: set break point (addr) reset break point (bp #) run write register (including sp and pc) dump registers dump mem (addr len)

I should also have support in the UART to go into breakpoint mode from inside getchar().

Step is just where you put a breakpoint on either the next assembly instruction or the first assembly instruction of the next C line, then erase it when done. In the case of conditional branches and returns, it’s a little tricker because they require either 2 breakpoints or evaluation of the condition flag to know where to put the next instruction. Also jp (hl) needs to be managed.

I just have to figure out how to use sdgdb….. Either that or make my own source debugger….

Progress

Thu, 01 Oct 2015 13:24:00 -0700

It took me a little while to figure out why my bank wasn’t running. asm(“call 4030”) does not output machine code that jumps to 0x4030–it jumps to 4030 or 0x0fbe. That’s wrong. So I added in the “0x” and all was well.

So now I am starting to wrap up a refactoring exercise.

I added a block that will go in all 16 sections. Each will have a pointer at 0x0026 that will point to this block.

 1 #define BANKINFO_TYPE_UNKNOWN ((uint8_t)0x00)
 2 #define BANKINFO_TYPE_CVECTOR ((uint8_t)0x01)
 3 #define BANKINFO_TYPE_APPLET ((uint8_t)0x02)
 4 #define BANKINFO_TYPE_EXECUTABLE ((uint8_t)0x03)
 5 
 6 // Every bank has a pointer at 0026 that points to a const BankInfo* _BANK_INFO; both crt0.s and crt1.s
 7 // expect a _BANK_INFO to be defined. This will typically be where main is defined.
 8 
 9 typedef struct BankInfo {
10     uint16_t CVersion; // 0{ix} 1(ix)
11     const char* Name; // 2{ix} 3(ix)
12     const char* TimeStamp; // 4{ix} 5(ix)
13     uint8_t Flags; // 6{ix}
14     uint8_t Type; // 7(ix) 1=c vector, 2=applet, 3=bank
15     uint16_t W0102; // 8{ix} 9(ix) // valid only is this is 0102
16     uint16_t W0304; // 10{ix} 11(ix)
17 } BankInfo;

This will be used for listing the contents of the flash. There will be 3 types of flash banks:

C Vector: These have the C library and drivers that the applets can use. But they don't really need anything else.
Applet: These will run the programs that I want to run
Executable: These will run standalone programs or menu items.

The applets require that they are linked with crt1.rel. The others with crt0.s. The C vectors need to link in c_vector.c.

At this point, I have to start reserving certain banks: 00: flash bank 0 is always run from reset. It will have a standalone executable with complex menu, but no c vector 01: flash bank 1 is always in bank 1 from reset. It will always be available for bank 00 to be able to hold programs larger than 16K. 10: RAM bank 10: This will be placed in bank 2 (i.e. 0x8000-0xbfff). It is there by default 11: RAM bank 11: This will be placed in bank 2 (i.e. 0xc000-0xffff). It is there by default

12: RAM bank 12: RAM bank 12 will be the standard bank for run from RAM in bank 0 (i.e. 0x0000-0x3fff)

13: RAM bank 13: RAM bank 13 will be the standard bank for run from RAM in bank 1 (i.e. 0x4000-0x7fff)

14: RAM bank 14: will be used for the standard bank that holds the C vector (0x0000-0x3fff)

I had to deal with the fact that the BankInfo block may be placed in blocks other than the block it expects, so the pointers to strings also have to point to the proper location.

All this bank switching has my brain running in circles, but it's finally getting into shape.